FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems

Abstract

Combinatorial optimization problems (COPs) are ubiquitous in applications such as finance, logistics, drug discovery, supply chain optimization, and public transportation. However, many COPs are non-deterministic polynomial-time hard (NP-hard), which require significant computation costs using conventional computers. Recently, Ising machines based on quantum annealing [1] and CMOS technologies [2]–[5] have received growing interest as efficient hardware accelerators that could replace traditional computing hardware (CPUs and GPUs) for solving real-world COPs. An Ising model, a basis of the Ising machines, finds the optimal (or sub-optimal) solutions of the COPs by efficiently exploring a solution space based on its intrinsic convergence property towards the lower Ising Hamiltonian (or energy). Another critical enabler is the annealing process, which prevents the Ising machine from converging to local minimum solutions and increases the chance to find the global optimum. Existing Ising machines with fixed hardware topology based on simple graphs (e.g., King's graph [2] [4]) are ill-suited to a practical Ising model with arbitrary spin interactions. In contrast, a fully connected Ising machine [3] can map a wide range of Ising models, but at the cost of significant overheads in area, power consumption, and latency. A recent work [5] demonstrated a reconfigurable Ising machine that enables an arbitrary interaction between spins. However, it has a restricted number of interactions per spin (up to 8) due to the fixed hardware topology (King's graph), which only allows eight interactions. In this paper, we propose an Ising machine that allows up to 28 arbitrary spin interactions based on flexible spin processing element (PE) circuits with temporal reconfigurability (i.e., multi-cycle operations with decomposed spin maps) to overcome the limited spatial spin interactions of the prior CMOS Ising machines. The proposed Ising machine with multi-spins embedded in each PE and multi-chip spin operations provides a scalable solution for solving the more complicated COPs.