Flexible Virtual Channel Power-Gating for High-Throughput and Low-Power Network-on-Chip

Abstract

Power-gating is a representative circuit level technique to mitigate leakage power. While in low-power Network-on-Chip (NoC) design, the former fine-grained power-gating methods will decrease network performance due to serial wake-up latency and head-of-line blocking. Therefore, we propose a flexible Virtual Channel (VC) management scheme for fine-grained power-gating to achieve high throughput and low-power. The proposed power-gating method with the early wake-up is evaluated by using some synthetic workloads. When compared with an optimized early wake-up power-gating technique, it can improve performance effectively in medium and high network loads, and increases the network throughput by 15.7%~44.1% for different synthetic loads, while keeps network power consumption as low as the optimized method. For the PARSEC application traces of token based protocol, it can significantly decrease packet latency by 20.3% on average, however only increases less than 3.6% peak power when compared with the optimized method.