Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis

Abstract

This paper presents a heuristic technique based on Particle Swarm Optimization (PSO) for finding the router positions from the available positions within the chip floor plan, so that the communication cost between cores is minimized, satisfying link length and router port constraints. Comparison with regular mesh-based NoC architectures and with custom architectures having routers positioned at the corners of the cores have been carried out. The results show significant reduction in communication cost.