Abstract
Subword parallel (SWP) architectures for Galois field multiplication and division over GF(2m) to meet the flexibility against performance requirements of an application-specific instruction set processor for applications within the domain of GF(2m) are presented. Suitable choices of basis, algorithm and architecture are addressed. Techniques for mapping an underlying Galois field arithmetic operation into these SWP architectures are described in the context of suitable well-known GF(2m) division and multiplication algorithms. The results of a detailed complexity analysis undertaken to quantify the configuration overheads as well as employing these in a SWP processor for cryptography are presented.
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