Flexible Controller Design and Its Application for Concurrent Execution of Buffer Centric Dataflows

Abstract

This paper presents a flexible controller structure for concurrent processing of memory centric coarse grain data flows. We propose a design flow based on block level pipelining where concurrency among processing blocks is fully maintained. The controller is dynamically reconfigurable to support dynamic data-flow structure changes by localizing control signals. The proposed control design method isolates controllers and processing logics such that system integration is simplified while controllers are locally configured from orthogonal global information. The controller also supports interfacing with external processors for asynchronous processing. The controller for heterogeneous processing blocks is synthesized and verified using Verilog and SystemC on FPGA. We present an example demonstrating the effectiveness of the controllers where dynamic reconfiguration of the execution is feasible.