Abstract
After discovering that the annealing-time dependence of the flatband voltage shifts of a p/sup +/-polysilicon gate MOS diode can be attributed to boron activation in polysilicon instead of boron penetration through gate M/sub 2/, we proposed a boron activation model for polysilicon in which the carrier activation is related to the grain size of the polysilicon. Using this model, we analyzed the characteristics of pMOSFETs with polysilicon gates of different grain sizes and found that they depend on the grain size, as expected. Using the model, we quantitatively identified process windows for p/sup +/-polysilicon gate pMOSFETs, assuming that enough boron is activated in the polysilicon without the boron penetrating through the gate SiO/sub 2/.
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