Fixed-Width Multiplier with Simple Compensation Bias

Abstract

Multiplications in many of the DSP applications are implemented by fixed-width multipliers primarily due to its low hardware complexity, less operation delay time and reduced power consumption. This paper presents an error compensation method for a fixed-width multiplier that receives two n-bit inputs and produces n-bit product. For the generation of error compensation bias, Booth encoder outputs have been employed. In order to compensate for truncation error and to generate the error compensation bias efficiently, truncated bits are divided into two groups and the carry estimation is done through exhaustive simulations. The simulation results reveal that the proposed method reduces the truncation error significantly compared with the direct-truncated multiplier with modest hardware overhead. Results further validate that the overall truncation error is significantly reduced as compared with the other existing method.