Fixed-priority scheduling to reduce both the dynamic and leakage energy on variable voltage processors

Abstract

With ever-scaling VLSI technology, the leakage is becoming an increasingly serious concern when addressing the power consumption problem for next-generation real-time embedded systems. Dynamic voltage scaling (DVS) is efficient in reducing the dynamic energy consumption of a CMOS processor. However, methods that employ DVS without considering the leakage current are quickly becoming less effective in reducing the processor's overall energy consumption. To be globally energy-efficient, the processor may have to run at a higher-than-necessary speed, which will cause a large number of idle intervals. While the processor can be shut down during these idle intervals to save energy, this process may incur significant timing and energy overhead. In this paper, we propose a DVS scheduling technique for fixed-priority hard real-time systems that can judiciously merge the short, scattered idle intervals into longer ones to reduce the shut-down overhead. The proposed technique has very low online computation complexity and can be readily incorporated with a variety of DVS scheduling techniques. Experimental results demonstrate that proposed technique can reduce the number of idle intervals and the overall energy consumption significantly more than conventional scheduling techniques.