Abstract
Time-domain back-projection (BP) is a widely known method used in synthetic aperture radar (SAR) image formation. Despite its advantages over other image formation algorithms, the BP method is hindered due to its computational complexity and its requirement of higher number of operations and processing power. Recently, field-programmable gate array (FPGA) devices have been used for BP acceleration mainly due to their parallel processing capabilities, reconfigurability, scalability, and low power requirement. This article presents a new fixed-point based BP (FxBP) design for FPGA devices and a floating-point-based BP (FlBP) design to compare performance. Both designs are developed with N -dimensional range (NDR) structure and single-work item (SWI) structure using OpenCL. The FPGA performance is evaluated using an FPGA performance metric. It is shown that FxBP-NDR and FxBP-SWI designs generate high-quality back-projected images compared to FlBP designs, while saving 16.87% and 42.54% on logic resources and gaining 17.90% and 91.62% on FPGA performance in NDR and SWI, respectively. Obtained results clearly indicate that FPGA devices perform significantly better with FxBP designs compared to FlBP designs, even with hardened FPUs.
Highlights
S YNTHETIC aperture radar (SAR) systems are used to obtain high-resolution imagery of various targets
The floating-point-based BP (FlBP) algorithm is designed with N-dimensional range (NDR) and single-work item (SWI) kernel structures to compare with the fixed-point based BP (FxBP) designs
It is shown that the FxBP designs save a significant amount of resource utilization compared to FlBP designs
Summary
S YNTHETIC aperture radar (SAR) systems are used to obtain high-resolution imagery of various targets. There are few frequency domain SAR algorithms (such as CS algorithm) developed as fully and partially fixed-point-based algorithms to target field-programmable gate array (FPGA) devices for real-time processing [18]–[20]. In the past two decades, many BP algorithms have been designed to accelerate the SAR image formation process Most of these methods are derived by modifying the traditional BP algorithm. Even though most of the accelerated BP algorithms are modified from the traditional BP algorithm, few methods use hardware acceleration from devices like general purpose graphics processing unit (GPGPU) [31]–[34] and FPGA [35], [36]. Since FPUs reduce the logic requirement, floating-point-based designs are used to process many computationally intensive algorithms on FPGA accelerators. The FxBP method is developed for spotlight SAR geometry by modifying the floating-point-based BP (FlBP) algorithm described in [29].
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