Fixed-point digital processing of recursive least-square algorithm toward FPGA implementation of MMSE adaptive array antenna

N Matsumoto,H Arai,K Ichige

doi:10.1109/isspa.2003.1224954

Fixed-point digital processing of recursive least-square algorithm toward FPGA implementation of MMSE adaptive array antenna

N Matsumoto, H Arai + Show 1 more

https://doi.org/10.1109/isspa.2003.1224954

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Publication Date: Jan 1, 2003

Citations: 3

Affiliation: Yokohama National University

#Recursive Least Square Algorithm #Recursive Least Square + Show 8 more

Abstract
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Abstract

In this paper, we try to implement RLS (recursive least square) algorithm on FPGA with fixed-point operation to be used in 4- elements MMSE (minimum mean square error) adaptive array antenna. RLS algorithm is known to the fast convergence property and broadly used in the optimization process of MMSE adaptive array. An inherent problem of RLS algorithm is the large computational cost. Hence it was difficult to implement on fixed-point DSP (digital signal processor) or FPGA (field programmable gate array). However, the computation must be simplified for the case with small number of array elements. Through some simulations with 4-elements array antenna, we confirm that RLS algorithm can be accurately implemented on fixed-point digital processors.

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