First-Principles Simulations of FETs Based on Two-Dimensional InSe

Abstract

We explore the performance limits of monolayer InSe ${n}$ -type and ${p}$ -type FETs by means of first-principle simulations of carrier transport in nanoscale devices. We evaluate the impact on device performance of different device parameters, such as channel length, oxide thickness, and gate underlap. Finally, we assess the operation of a 32-bit CMOS ALU, based on InSe FETs with 10-nm channel length, for both high-performance and low-power applications, and find promising figures of merit with respect to CMOS and other beyond-CMOS proposals.