First implementation of the MEPHISTO binary readout architecture for strip detectors

Abstract

Today's front-end readout chips for multi-channel silicon strip detectors use pipeline-like structures for temporary storage of hit information until arrival of a trigger signal. This approach leads to large-area chips when long trigger latencies are necessary. The MEPHISTO architecture uses a different concept. Hit strips are identified in real time and only the relevant binary hit information is stored in FIFOs. For the typical occupancies in LHC detectors of ≈1 hit per clock cycle this architecture requires less than half the chip area of a typical binary pipeline. This reduces the system cost considerably. At a lower data rate, operation with very long trigger latencies or even without any trigger is possible due to the real-time data sparsification. The Mephisto II architecture is presented and the expected performance is discussed.