First Demonstration of Ferroelectric Tunnel Thin-Film Transistor Nonvolatile Memory With Polycrystalline-Silicon Channel and HfZrO Gate Dielectric

Abstract

In this work, the nonvolatile memory constructed on the tunnel thin-film transistors (tunnel-TFTs) using polycrystalline-silicon channel featuring ferroelectric HfZrOx layer is demonstrated for the first time. When the pulse voltages of program (PG) and erase (ER) are, respectively, 3.5 and −2 V with the pulsewidth of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1 ~\mu \text{s}$ </tex-math></inline-formula> , the threshold voltage modulation amount of the ferroelectric tunnel-TFT can reach −0.524 and 0.496 V, respectively. In addition, the endurance behaviors of the ferroelectric tunnel-TFT exhibit a strong PG/ER pulsewidth dependence. The wake-up effect of the ferroelectric layer becomes more pronounced as increasing the PG/ER pulsewidth. Moreover, the increase of the PG/ER pulsewidth also causes the ferroelectric tunnel-TFT to be subjected to the electrical dynamic stress effect, leading to the degradation of the subthreshold swing (SS) and the electron trapping effect. When the pulsewidth is 100 ns, the endurance is mainly dominated by the fatigue effect of the ferroelectric layer and the degradation of the SS. When the pulsewidth increases to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1 ~\mu \text{s}$ </tex-math></inline-formula> , the endurance is mainly dominated by the electron trapping effect of the ferroelectric layer in addition to the fatigue effect. The retention of the ferroelectric tunnel-TFT exhibits stable behavior at 50 °C. Consequently, the ferroelectric tunnel-TFT exhibits sufficient electrical performance and can be integrated with display panels and various sensor systems on smart wearable devices for edge computing applications.