Abstract
The Tile Computer on Module (TileCoM) mezzanine board is one of the auxiliary boards of the Tile PreProcessor (TilePPr) for the Phase-II Upgrade of the readout electronics of the ATLAS Tile Calorimeter (TileCal). This board will be responsible for system monitoring and configuration by interfacing the Trigger Data Acquisition (TDAQ) system and the TilePPr. Features include configuration and monitoring of the Advanced Telecommunications Computing Architecture (ATCA) carrier and Compact Processing Module (CPM) onboard sensors through I2C and Gigabit Ethernet. This contribution presents firmware developments on an embedded Linux for the ZYNQ System-on-Chip (SoC) targeting an Avnet Ultra96-V2 ZYNQ UltraScale+ MPSoC evaluation board. This test bench will serve as a basis for the development of the main functionalities of the TileCoM mezzanine board to interface the TilePPr with the Detector Control System (DCS) and the TDAQ-I system of the Tile Calorimeter.
Highlights
Tile Calorimeter (TileCal) aged legacy electronics will not be able to withstand the new radiation requirements of the High Luminosity Large Hadron Collider (HL-LHC)
Features include configuration and monitoring of the Advanced Telecommunications Computing Architecture (ATCA) carrier and Compact Processing Module (CPM) onboard sensors through I2C and Gigabit Ethernet. This contribution presents firmware developments on an embedded Linux for the ZYNQ System-on-Chip (SoC) targeting an Avnet Ultra96-V2 Zynq UltraScale+ MPSoC evaluation board. This test bench will serve as a basis for the development of the main functionalities of the Tile Computer on Module (TileCoM) mezzanine board to interface the Tile PreProcessor (TilePPr) with the Detector Control System (DCS) and the Trigger Data Acquisition (TDAQ) system of the Tile Calorimeter
To provide monitoring data to the DCS through the Open Platform Communications (OPC) Unified Automation (UA) server implemented on the ARM processor of the Zynq SoC
Summary
To remotely program the on- and off-detector FPGAs by sending bitstreams through the Xilinx Virtual Cable. To provide slow control and configuration capabilities; including an interface with the TDAQ to monitor and configure the TilePPr and the on-detector electronics. To provide monitoring data to the DCS through the Open Platform Communications (OPC) Unified Automation (UA) server implemented on the ARM processor of the Zynq SoC
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