Abstract
The Belle II experiment with SuperKEKB accelerator has started beam collision in 2018. With a higher luminosity, the target of Belle II is to improve the measurement of rare B meson decays and to probe for new physics. The present DAQ system in Belle II is designed to operate under a maximum trigger rate of 30 kHz at expected peak luminosity, and its stability has been confirmed in the early phases of the operation so far. Considering the difficulty of maintenance and the limited performance of the current read-out system, Belle II DAQ group is preparing an upgrade by using PCI-express-based readout board (PCIe40) which is capable of a higher data throughput of 100 Gb/s. PCIe40 board is based on an Intel Arria 10 field-programmable gate array, which has 48 transceivers and PCI-express DMA architecture. The PCIe40 firmware for Belle II needs to have many functionalities, such as custom Belle2Link protocol to detector Front-End, interface to trigger and timing distribution system, data processing logic for first-level event building, and DMA implementation. This paper describes the development of each item and performance tests with various Belle II detectors’ Front-End electronics (FEE), as well as the plan of integrating the new readout system in the Belle II global DAQ system.
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