Abstract
The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector has inserted an additional inner layer called the Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL's off-detector DAQ system. The strategy for IBL ROD firmware development was three-fold: keeping as much of the Pixel ROD datapath firmware logic as possible, employing a complete new scheme of steering and calibration firmware, and designing the overall system to prepare for a future unified code version integrating IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBL DAQ test bench using a realistic front-end chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBL ROD data path implementation, test on the test bench and ROD prototypes, will be reported. Recent Pixel collaboration efforts focus on finalizing hardware and firmware tests for the IBL. The plan is to approach a complete IBL DAQ hardware-software installation by the end of 2014.
Highlights
The Readout-Driver card (ROD) cardThe ROD design features modern FPGA Xilinx devices: one Virtex-5 master device for control and two Spartan-6 slaves dedicated to data processing (gathering of front-end output, event building, and calibration data processing)
The Readout-Driver card (ROD) design features modern FPGA Xilinx devices: one Virtex-5 master device for control and two Spartan-6 slaves dedicated to data processing
- firmware upload from VME, JTAG ports, - Back-of-Crate card (BOC)-2-ROD dataflow, - BROD-2-Trigger-and-Control Interface Module (TIM) communication, - R/W tests for Virtex[5] and Spartan[6] on-board memory modules, - dataflow tests on the 3 Gb/s ports In particular the ROD firmware upload includes a configuration via VME of the firmware and software for embedded processors
Summary
The ROD design features modern FPGA Xilinx devices: one Virtex-5 master device for control and two Spartan-6 slaves dedicated to data processing (gathering of front-end output, event building, and calibration data processing). The VME bus interfaces the ROD with the DAQ controller system, acting as a backup to the main control link (Gigabit Ethernet) and allowing for remote upload of the FPGA’s firmware. Other ROD external ports are: a Gigabit Ethernet towards the DAQ controller system (main connection), two Gigabit Ethernet ports to deliver the calibration scan results, one TTCrq mezzanine (port interface) to receive ATLAS clock and trigger commands, and four custom buses to the BOC through VME connectors. VHDL blocks in the figure have the task to readout the front-end chips and format the event data
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