Abstract
ATLAS is one of the four big LHC experiments and recently its Pixel Detector was upgraded with a new innermost 4th layer: the Insertable B-Layer (IBL) . The upgrade will result in better tracking efficiency, improved precision of measurements and, in the future, compensation for radiation damage of the Pixel-Detector. Newly developed front-end electronics and the higher than originally planned LHC luminosity required a complete re-design of the Off Detector Electronics consisting of the Back Of Crate card (BOC) and the Read Out Driver (ROD) . The main purposes of the BOC card are the distribution of the LHC clock to all Pixel Detector components as well as interfacing the detector and the higher level readout optically. The data-path to the detector runs a 40 MHz bi phase mark (BPM) encoded stream. The 160 MHz 8b10b encoded data path from the detector is phase and word aligned in the firmware and then forwarded to the ROD after decoding. The ROD will send out the processed data that is then forwarded to the higher level readout by the BOC card. An overview of the newly developed firmware will be presented together with the results from production tests and the system test at CERN . Focus is put on the partial reconfiguration and results of the fine delay measurements.
Highlights
The new Insertable B-Layer (IBL) Back-Of-Crate card (BOC) card is equipped with three modern Xilinx Spartan-6 FPGAs for signal processing: BOC Control FPGA (BCF): slow control interfaces from the ROD and the Gigabit Ethernet connection. Two BOC Main FPGAs (BMF): signal processing and monitoring of incoming data
The new IBL BOC card is equipped with three modern Xilinx Spartan-6 FPGAs for signal processing:
The data flow from the optoboards runs through optical fibers to a card pair consisting of the Read-Out-Driver (ROD) and the Back-Of-Crate card (BOC)
Summary
The new IBL BOC card is equipped with three modern Xilinx Spartan-6 FPGAs for signal processing: BOC Control FPGA (BCF): slow control interfaces from the ROD and the Gigabit Ethernet connection. Two BOC Main FPGAs (BMF): signal processing and monitoring of incoming data. The new IBL BOC card is equipped with three modern Xilinx Spartan-6 FPGAs for signal processing: BOC Control FPGA (BCF): slow control interfaces from the ROD and the Gigabit Ethernet connection. Transmitters (Tx): 40 - 80 - 160 Mbps. Modules on staves are electrically connected to optoboards that handle the electrical-optical conversion. The data flow from the optoboards runs through optical fibers to a card pair consisting of the Read-Out-Driver (ROD) and the Back-Of-Crate card (BOC). The ROD handles the detector calibration and data taking, the BOC behaves as interface with the detector and to the higher level read-out (ROS). The BOC card distributes the LHC clock from the Timing-Trigger Control Interface Module (TIM) to the ROD and to the detector.
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