FINITE ELEMENT MODELING OF HEAT TRANSFER IN CHIP ON TAPE PACKAGES

Abstract

Listen

Translate article

In the electronic industry, numerical modeling using the finite element method (FEM), is an effective way to predict thermal performance of ICs in the initial stage of package development. Moreover, thermal simulation can provide a greater understanding of the physics of the problem, allowing designs to be optimized quickly and cheaply, thereby keeping expensive experimental measurements to a minimum. In this study, 3-D thermal models capturing the details of the leadframe and internal structure of the chip on tape (COT) packages was developed using a commercial FEM simulation code MARC. Finite element model results of thermal performance of COT packages under various specified external flow conditions and power dissipation are presented. Steady state numerical calculations were performed to determine the junction temperature and thermal resistance of complex COT packages. The complex heat flow patterns within the 3-D packages were established and compared with the experimental results.7,8 Moreover, the effect of package layout, die attach materials, and COT leadframe materials on the thermal performance of COT packages were studied. The results show that the addition of die attach material in COT packages enhance the heat transfer from the die, especially with the help of the spreader on the substrate. The use of with die attach materials higher thermal conductivity and leadframe also significantly contributed to enhanced thermal performance. Finally, the heat dissipation of COT packages was also found to be affected by the circuit contents on the FR-4 board (substrate).