Finite-Element Analysis and Experimental Test for a Capped-Die Flip-Chip Package Design

Abstract

In flip-chip packages, the coefficient of thermal expansion (CTE) mismatch between the chip and the substrate is the root cause for reliability issues such as excessive warpage, low-k dielectric layer cracking, solder mask cracking, and bump cracking. The first and foremost thing in designing a flip-chip package is to meet the warpage specification. This paper proposes a capped-die flip-chip package to control the warpage as well as to reduce the stress in solder bumps. In the capped-die flip-chip package, a metal cap tightly covers and bonds with the die through an adhesive material, leading to a capped die with a higher effective CTE. By adjusting the thickness of the metal cap, the effective CTE of the capped die may match with that of the substrate, theoretically achieving zero warpage or warpage free. Guided by finite-element analysis, a 45 × 45-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> size of capped-die flip-chip package was manufactured, and a copper die cap with 0.4 mm thickness is selected to verify this concept. Shadow Moiré test data showed that in the temperature range from 25 °C to 260 °C, the warpage curve of the capped-die package is almost flat and close to zero, confirming the cappeddie concept. Furthermore, finite-element modeling was used to investigate the stress in bump, as well as the thermal performance of the capped-die flip-chip packages. It is found that thermal performance of the capped-die package can be good enough for high-power applications. The bump stress of the capped-die package is about 50% lower compared to the lidded package. The applications of the capped-die package design in coreless substrate packages are also discussed in this paper.