Finite Element Analyses for Critical Designs of Low-Cost Wafer-Level Chip Scale Packages

Abstract

With the advantages of high performance and low cost, the wafer-level chip scale package (WLCSP) is widely used in integrated circuit fabrication today with rapidly growing demand in the semiconductor packaging industry. As WLCSP moves toward thinner, smaller, lower cost, and fine-pitch package designs to meet the increasing requirements of electronic products, a lot of challenges need to be overcome. The most important challenge is preventing failure and enhancing package reliability. To understand the mechanical behaviors of WLCSP, comprehensive finite-element analyses (FEAs) for various WLCSP structures, including the general design with one under-bump-metallurgy layer, one redistribution layer (RDL), and two polymer layers on a passivated wafer (called 2P2M WLCSP in this paper, which means that there are two polymer layers and two metal layers on the passivated wafer), the low-cost designs of 2P1M WLCSP (with two polymer layers and only one RDL on a passivated wafer) as well as 1P1M WLCSP (with only one polymer layer and one RDL on a passivated wafer) were carried out. Different parameters in WLCSP were investigated to look for critical factors that impact the corresponding stresses. Moreover, the board level reliability thermal cycling test that followed JEDEC standard was used, which suggested that the solder cracks were observed mostly near the intermetallic compound layer in WLCSP structures and aligned with the FEA results. Hence, by employing reliable modeling, not only can the critical factors that affect the stress responses be obtained but also can the proper parameters to provide the best reliability in WLCSP be determined. This paper offers a good reference and can effectively serve as design guidelines in cases of significant factor selection analyses on WLCSP designs.