Abstract
It took quarter of a century for multi-gate transistor to make it from first demonstration in research to a product - 22nm technology node microprocessor in 2012. FinFETs offer superior performance over incumbent planar devices due to their significantly improved electrostatics. FinFET technology faced two key barriers to their implementation in products: demanding process integration and its significant impact on layout and circuit design methodology. In this paper we focus on challenges and tradeoffs in both of these areas. Fin shape, pitch, isolation, doping, crystallographic orientation and stressing as well as device parasitics, performance and patterning approaches will be discussed. Implementation of high mobility materials for finFET devices will also be briefly reviewed as well as design challenges for logic and SRAM circuits.
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