Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks

Abstract

In this work, we demonstrate a novel unique design approach specifically targeting improved resilience against the fine-grained electromagnetic (EM) side-channel analysis (SCA) attacks. Fine-grained EM SCA captures high SNR EM signature with tiny probes (1mm diameter) compared to coarse-grained EM (∼10mm diameter), making it more potent and leading to a higher threat. The EM-SCA critical circuit blocks are voltage-stacked to share a current loop, and a push-pull voltage regulator (VR) balances the mismatch current between the two stacked blocks. Dataflow and current loops are spatially and temporally randomized to obscure the EM side-channel signatures. Measurement results from a 128-bit Parallel Advanced Encryption Standard (AES) core fabricated in 65nm CMOS shows MTD improvement of 1507X for fine-grained EM SCA. Coarse-grained EM and Power SCA MTDs also show an improvement of 122X and 657X respectively, which may be improved further by combining prior reported SCA resilient techniques.