Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing

Abstract

At speed Built-In Self Test (BIST) circuit can solve many test challenges generated from traditionally slower Automatic Test Equipment (ATE). In this paper, a double edge clipping technique is proposed for built-in at-speed delay testing requirements. It differs from traditional circuit delay testing techniques by changing the clock rate using external ATE. This method uses lower-speed input clock frequency, then applies internal BIST technique to adjust clock edges for circuit at-speed delay testing and speed binning. Test chips are fully validated. The fine-scale (16ps) progressive capture edge adjustment technique with high-precision (28ps) calibration circuit is effective for at-speed delay testing and performance binning.