Abstract
BackgroundMetaheuristics are widely used to solve large combinatorial optimization problems in bioinformatics because of the huge set of possible solutions. Two representative problems are gene selection for cancer classification and biclustering of gene expression data. In most cases, these metaheuristics, as well as other non-linear techniques, apply a fitness function to each possible solution with a size-limited population, and that step involves higher latencies than other parts of the algorithms, which is the reason why the execution time of the applications will mainly depend on the execution time of the fitness function. In addition, it is usual to find floating-point arithmetic formulations for the fitness functions. This way, a careful parallelization of these functions using the reconfigurable hardware technology will accelerate the computation, specially if they are applied in parallel to several solutions of the population.ResultsA fine-grained parallelization of two floating-point fitness functions of different complexities and features involved in biclustering of gene expression data and gene selection for cancer classification allowed for obtaining higher speedups and power-reduced computation with regard to usual microprocessors.ConclusionsThe results show better performances using reconfigurable hardware technology instead of usual microprocessors, in computing time and power consumption terms, not only because of the parallelization of the arithmetic operations, but also thanks to the concurrent fitness evaluation for several individuals of the population in the metaheuristic. This is a good basis for building accelerated and low-energy solutions for intensive computing scenarios.Electronic supplementary materialThe online version of this article (doi:10.1186/s12859-016-1200-9) contains supplementary material, which is available to authorized users.
Highlights
Metaheuristics are widely used to solve large combinatorial optimization problems in bioinformatics because of the huge set of possible solutions
Our work tries to get a wide insight into important aspects to take into account when designing accelerators. This way, our main contribution in this paper is to demonstrate that the fine-grained parallelization of fitness functions based on floating-point arithmetic can surpass the performance given by Central processing unit (CPU), in time and power terms, when they are massively used by metaheuristics for solving large combinatorial optimization problems in bioinformatics
Two case studies in bioinformatics We have tackled the implementation of the two above mentioned bioinformatics problems following the same strategy: first, we design a fine-grain parallel circuit that implements the fitness function; we measure the speed-up with regard to current general-purpose processors for just one fitness evaluation; we estimate the performance when several fitness circuits evaluate individuals in parallel, taking into account the area constraints for a single Field Programmable Gate Array (FPGA)
Summary
This section summarizes the tools, hardware resources, and implementation keys from which the results were obtained. The synthesis and implementation step allows obtaining the minimum clock frequency for a determined FPGA device Using this information, a VHDL testbench customized with the corresponding clock period can simulate the top level design using ISim, obtaining the time response of the circuit, which will be used to calculate the FPGA speedup. If we consider DSPs, the performance can be better, but the limited number of DSPs forces us to consider digital logic if we want to have more parallel units, involving more area consumption; this tradeoff between number and performance of parallel operators must be evaluated in each case This way, each design was synthesized up to 6 times (according to the 3 synthesis profiles and the 2 possibilities of using DSPs in the operator circuits), recording the best result among the obtained ones. The synthesis process tells us the power (watts) consumed by the fitness circuits
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