Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices

Abstract

In this brief, we present a fine-grained dark silicon architecture to facilitate further integration of transistors in static random access memory-based reconfigurable devices. In the proposed architecture, we present a technique to power off inactive configuration cells in nonutilized or underutilized logic blocks. We also propose a routing circuitry capable of turning off the configuration cells of connection blocks (CBs) and switch boxes (SBs) in the routing fabric. Experimental results carried out on the Microelectronics Center of North Carolina benchmark show that power consumption in configuration cells of lookup tables, CBs, and SBs can, on average, be reduced by 27%, 75%, and 4%, respectively.