Fine-Grain Register Allocation and Instruction Scheduling in a Reference Flow

Abstract

This paper proposes a new register allocation technique in which register allocation is performed at every reference of a variable. For each reference, the costs of various possible register allocations are estimated by tracing a possible instruction sequence. A cost model is formulated to reduce the scope of tracing. With an extension of the cost model to the estimation of instruction execution time, a new technique for the integration of instruction scheduling and register allocation is also proposed. Experiments show that the proposed register allocation and the integration techniques achieve significant improvements when compared with widely used existing techniques.