Fin Field Effect Transistors Performance in Analog and RF for High-k Dielectrics

Abstract

The high-k is needed to replace SiO 2 as the gate dielectric to reduce the gate leakage current. The impact of a high-k gate dielectric on the device short channel performance and scalability of nanoscale double gate Fin field effect transistors (FinFET) CMOS is examined by 2-D device simulations. DG FinFETs are designed with high-k at the high performance node of the 2008 Semiconductor Industry Association International Technology Roadmap for Semiconductors (ITRS). DG FinFET CMOS can be optimally designed to yield outstanding performance with good trade-offs between speed and power consumption as the gate length is scaled to < 10 nm. Using technology computer-aided design (TCAD) tools a 2-D FinFET device is created and the simulations are performed on it. The optimum value of threshold voltage is identified as V T =0.653V with e=23(ZrO 2 ) for the 2-D device structure. For the 2-D device structure, the leakage current has been reduced to 9.47×10 -14 A. High-k improves the I on /I off ratio of transistors for future high-speed logic applications