Abstract
Presents a method to realize FIR filter based on DSP Builder, FIR design using a relatively independent function of circuit module and subsystems in the design, it can easily realize the filtering function of FIR, simplified the design, modular design method greatly shortens the development cycle, make the system have been optimized in the chip area and timing analysis etc. Experimental results show that the filtering performance of the filter is good, and completely suitable for use in practical engineering in various signal processing.
Highlights
Digital filter can be divided into two categories according to the time domain characteristics of unit impulse response function: Infinite Impulse Response (IIR) filter and Finite Impulse Response (FIR) filter
The design method based on DSP chip adopt a unique internal hardware structure to realize the filtering algorithm, it need instruction programming and debugging online simulation real-time on DSP hardware, so the development process is very complex [4]; the design method based on MATLAB and DSP hardware aided design using MATLAB to extracting the filter coefficients, but needed to write special instruction code for digital signal processing on DSP, so dependency on hardware, poor portability; the design method based on FPGA chip uses the VHDL language for algorithm design, the hardware can be modified and the code does not depend on the chip, but the code simulation and debugging is relatively complex and the development cycle is relatively long [5, 6]
This method works in Simulink environment of MATLAB software, using Altera’s DSP Builder toolbox to realize system-level graphical model simulation, and generate VHDL code for FPGA download
Summary
Digital filter can be divided into two categories according to the time domain characteristics of unit impulse response function: Infinite Impulse Response (IIR) filter and Finite Impulse Response (FIR) filter. The design method based on DSP chip adopt a unique internal hardware structure to realize the filtering algorithm, it need instruction programming and debugging online simulation real-time on DSP hardware, so the development process is very complex [4]; the design method based on MATLAB and DSP hardware aided design using MATLAB to extracting the filter coefficients, but needed to write special instruction code for digital signal processing on DSP, so dependency on hardware, poor portability; the design method based on FPGA chip uses the VHDL language for algorithm design, the hardware can be modified and the code does not depend on the chip, but the code simulation and debugging is relatively complex and the development cycle is relatively long [5, 6]. This paper puts forward a design method based on DSP Builder. This method works in Simulink environment of MATLAB software, using Altera’s DSP Builder toolbox to realize system-level graphical model simulation, and generate VHDL code for FPGA download. The method can flexibly designed filter structure, and easy to develop, in addition easy function expansion and upgrading
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