Abstract
Back-gated field effect transistors (FETs) based on catalyst-free grown 3C-SiC nanowires (NWs) were fabricated and electrical characterization is presented. Silvaco simulation was used to fit the I-V characteristics and to extract information about the carrier (electrons) concentration and the oxide/NW interface quality. The high trap density and fixed charges at the nanowire/oxide interface, Dit~5x1011 cm-2eV-1 and Qf ~3x1013cm-2, and the high electron concentration (~3x1019 cm-3) originating from unintentional doping severely affect the electrical conduction through the nanowires which has as a result low values of mobility and transconductance, 0.11 cm2/Vs and 7x10-10 A/V, respectively.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
