Ferroelectric Thin Films and Thin Film Devices

Abstract

Research and development efforts on ferroelectric memories have been underway since about 1955. The early work, largely at IBM, RCA, Bell Telephone Laboratories and other US industrial laboratories was stymied by two problems: Firstly, the materials were too thick to permit operation at 5 V, the standard “TTL” or “CMOS” operating voltages in the silicon integrated circuit technology that dominates the microelectronics industry; and second, there is considerable “crosstalk” and unintentional switching of cells laid out in simple row-and-column matrix form. In the 1990s, however, the perspective is very different: Techniques for depositing very thin, pinholefree films have developed significantly in the past three decades; at present sputtering, sol-gel spinon, laser ablation, and various other techniques (MOD, MOCVD, etc.) can all be used to prepare optically uniform films over full 4′ to 6′ wafers, capable of withstanding 4 MV/cm or more. And the old problem of cross-talk or “half-select disturb pulses” has been circumvented by designing memory arrays in which each ferroelectric cell is isolated from its neighbors by one or two transistors (“IT” or “2T” DRAM architecture) or as many as six transistors (in a more conservative “6T” SRAM lay-out). As a result, there has been a renaissance of engineering interest in ferroelectric thin films.