FEROM, the ALICE SSD read out system

Abstract

The main FEROM (Front End Read Out Module) task is the digitalization of the 2.6 million SSD (Silicon Strip Detector) strip values in 160 μs. This is achieved by digitizing in parallel the 1698 double-sided SSD module signals (each containing 1536 strip values). The FEROM also performs the zero-suppression and offset correction, the event-data derandomization using Multiple Event Buffers (MEB) and the event data transfer to the DAQ. The FEROM system consists of 8 6U VME crates, each containing 216 ADCs. These crates also interface with the CTP (Central Trigger Processor), DAQ and DCS (Detector Control System). Special precautions are taken to reduce SEU problems. As the FEROM is installed in the cavern and inaccessible during beam-time, much emphasis has been put on high reliability design techniques. JTAG is used to check connectivity of the large number of cables that go to the detector. I. THE ALICE SSD SUBDETECTOR The ALICE SSD sub-detector consists of 1698 SSD modules. Each SSD module (see Figure 1) consists of a double-sided SSD with 1536 strips (786 strips per side) and 12 HAL25 front-end chips. Figure 1: SSD-module Each HAL25 [1] has 128 input-preamp-shaperSample/Hold circuits and an analog output multiplexer. The HAL25 has the following 5 control signal inputs: HOLD, RCLK (Read Clock), TK_IN (Token in), FSTRB (Fast Reset) and PULSE. The HOLD-input controls all 128 Sample/Holdcircuits in parallel. Under control of RCLK, TK_IN and FSTRB the analog output multiplexer forwards one of the 128 S/H circuit outputs to the HAL25 differential analog output buffer. A token passing mechanism allows the analog output buffers of several HAL25 chips to be connected together. This is achieved by daisy-chaining the HAL25 TK_IN and TK_OUT signals. The FSRTB can be used for resetting the output multiplexer, which is useful for quickly terminating the readout, e.g. in case of an L2r (=level 2 trigger reject). The PULSE input injects a specific charge into one of the input channels, which can be used for test and calibration purposes. Each HAL25 also has a JTAG port, which can be used for control tasks like setting shaping time, setting the test-PULSE channel and bypassing the token when the HAL25 chip does not operate in a proper way. Figure 2: The ALICE SSD sub-detector: ITS layer 5 & 6. The 1698 SSD modules are mounted on 72 ladders, forming two cylindrical silicon layers surrounding the interaction point. They are layer 5 and 6 of the ALICE ITS (Inner Tracking System). Each ladder end has an ECM (End Cap Module [2]), which provides the interconnection between the outside world and the (10...13) SSD-modules on a half ladder. Layer 5 ladders have 22 SSD-modules where 10 modules are connected to the ECM on one side and 12 modules to the ECM on the other side. For layer 6 (25 modules), these figures are 12 and 13. Each ECM has a JTAG interface (for front-end configuration and interconnectivity check), readout out control lines (5) and (10...13) SSD-module analog output lines. The HAL25 token mechanism allows the ECM to have one analog output for each SSD-module. During readout, each analog output shows sequentially in time the 1536 strip values of the corresponding SSD-module. The ECM also has an error output signal to indicate token errors and power supply problems. The ECM also takes care of the double-sided SSD bias voltage difference by using a ground level separator. Table 1: Numbers about ladders, ECMs, SSDs and strips. Layer # ladders # ECMs #SSD/ ladder #SSD #Strips 5 34 68 22 748 1148928 6 38 76 25 95