Abstract
Since interconnects play the increasingly important role in delay and area of the Field-programmable gate array (FPGA) implementations, routing architecture design has become the focus of much work related to FPGA architecture development. This paper leverages feedforward neural networks to derive accurate models of the routing channel width in homogeneous FPGA architecture with two advanced intelligence learning techniques: Gradient-based learning algorithm (GLA) and Extreme learning machine (ELM). The resultant models can be used in the early stages of FPGA architecture development to facilitate fast design space exploration which is difficult to achieve in the traditional experiment-based method. The proposed models are evaluated by comparing the estimated channel widths to the real values generated from a CAD tool VTR over IWLS2005 benchmark circuits. Results show that the GLA model achieves the estimation accuracy 3.98% and the ELM model has the accuracy 3.91%, which show significant improvement over existing estimation approaches.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.