Feasibility study of the application of voltage contrast to printed circuit board

Abstract

Voltage contrast (VC) has been a powerful tool for the failure analysis of integrated circuits and multichip module. As the packing density of printed circuit board (PCB) is increasing, conventional failure analysis methods to detect open or short circuit in PCBs are no longer adequate, and voltage contrast method could be a method for this purpose. However, unlike the cases of integrated circuits and multichip module, there are many areas in PCB that will produce serious charging effect when examine under the scanning electron microscope. One of the areas is the presence of solder mask on PCB. This work examines the feasibility of using voltage contrast for PCB failure analysis. Specially designed PCB is used for experimentation, and it is found that positive bias on one track and zero bias on another copper track provide a better image contrast as compared to negative and zero biases on the tracks. Also, the variation of the image contrast with different spacing between inter copper tracks has studied. It is found that the variation depends on the presence of solder mask and its location. The variation can be very different for negative bias case as compared to the positive bias case. Finite element analysis is also performed to explain the experimental observations. All the observations can be well explained by the charging effect of the solder masks. The charging effect of solder mask is indeed very significant in affecting the image contrast, and it could reduce the contrast to almost zero in some cases.