Abstract

The feasibility of sub-100 nm patterning with ArF lithography has been studied. We used ArF 0.63 NA exposure tool and investigated process windows. In-house resist (DHA-H110) and bottom anti-reflective coating material (HEART004) are used as well as commercial ones. To print sub-100 nm patterns we used the resolution enhancement technology (RET) that is extreme off-axis illumination (OAI) such as dipole and strong annular. To predict the result and compare with experimental data our simulation tool HOST (Hyundai OPC Simulation Tool) based on diffused aerial image model (DAIM) was used. Although the infrastructure of ArF lithography is not mature enough, we got a good result. For 95 nm and 90 nm patterns we could get more than 8% exposure latitude (EL) and 0.3 micrometer depth of focus (DOF). For isolated gate pattern sub-70 nm pattern was printed and we have got the characteristics of 70 nm periphery transistor. For contact hole (C/H) patterns it was more effective to use KrF lithography because resist thermal flow process (RFP) can be used to shrink C/H size. With RFP we printed up to 50 nm C/H patterns. Through this study we found that k1 value can be reduced up to 0.29 and ArF lithography can be applied for 70 nm node with high contrast resist and high NA exposure tool.

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