Feasibility Demonstration of Server Chip Package With Direct-to-Chip Optical Transceivers

Abstract

Abstract Fiber optic interconnect provides unique advantage over to copper signaling including: 1) Optical links are more capable of transmitting high speed signals over a longer distance than copper cable. The latter usually requires high power for distant transmission. 2) Low power optic interface enables to lower the overall system power. 3) Higher input/output density can be achieved through optical fibers than copper wires. Optical transceivers are typically designed for integration at printed circuit boards (PCB) level. However, driving signal from packaged processor chip, through processor interconnect and across PCB causes significant signal integrity challenges. Co-packaging solution with the optical transceiver integrated on processor module and with direct-to-substrate cabling enables high-speed signals by avoiding the PCB altogether. The challenge lies in adapting the optical transceiver for compatibility with the processor module structure, as well as the environmental exposures of both the processor module bond and assembly process and system application condition. This paper focuses on the assembly, characterization, and reliability stress results of an array of optical transceivers co-packaged within single chip processor module. The co-package studied is a 76.5mm × 68.5mm flip chip packaging with 4 or 5 optical transceivers assembled on the chip carrier substrate. A chip package interaction (CPI) test chip was mounted on laminate along with the connectors using traditional bond and assembly (BA) processes and fixtures. This was followed by lidding with a Thermal Interface Material (TIM) between the test chip and copper heat spreader, and a separate TIM between optical transceivers and heat spreader, and an elastomer structural bond between the laminate and the heat spreader. The co-packaged module was then tested, land grid array (LGA) socketed to a thermal card for power and signal connection. Examination of the thermal performance and structural integrity after 1000 cycles of deep thermal cycling (DTC), Shock and Vibration (S&V), Temperature and Humidity testing, and High Temperature Storage (HTS) will be discussed. Characterization and construction analysis of the package, and model and data comparison with traditional packages will be presented.