FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

Abstract

We report FDSOI devices with a 20nm gate length (L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> ) and 5nm spacer, featuring a 20% tensile strained Silicon-on-Insulator (sSOI) channel NFET and 35% [Ge] partially compressive strained SiGe-on-Insulator (SGOI) channel PFET. This work represents the first demonstration of strain reversal of sSOI by SiGe in short channel devices. At V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> of 0.75V, competitive effective current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</inf> ) reaches 550/340 µA/µm for NFET, at I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> of 100/1 nA/µm, respectively. With a fully strained 30% SGOI channel on thin BOX (20nm) substrate and V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> of 0.75V, PFET I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</inf> reaches 495/260 µA/µm, at I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> of 100/1 nA/µm, respectively. Competitive sub-threshold slope and DIBL are reported. With the demonstrated advanced strain techniques and short channel performance, FDSOI devices can be extended for both high performance and low power applications to the 10nm node.