FDSOI circuit design for high energy efficiency: Wide operating range and ULP applications - a 7-year experience

Abstract

With the increasing complexity of today's MPSoC and IoT applications, extremely high performance has become the main requirement. However, high performances do not only mean high speed but also low power. The compromise between high speed and low power is very difficult to reach with today's technologies. Most of the time, ultra low power architectures cannot reach high speed and conversely, at high speed, a lot of power is consumed. The need to increase speed at low voltage while maintaining very high speed at nominal voltage is still a key issue. This talk will address the design of Ultra Wide Voltage Range (UWVR) systems using thin-film planar FDSOI devices. This compelling technology appears to meet the needs of nomadic devices, combining high performance and low power consumption. A major challenge for this technology is to provide various device threshold voltages (VT), trading off power consumption and speed. The efficient use of an adaptive voltage and frequency scaling architecture combined with efficient Back Biasing will be detailed and silicon results provided for many different digital blocks designed during the past 7 years in the context of high speed multicores and low power IoT end-devices.