Abstract
The main challenge of Low Temperature (LT) Solid Phase Epitaxy (SPE) is the dopant deactivation during post activation anneal. For the first time, we demonstrate that, for LT-SPE activated Boron (B) on thin SOI substrates, B deactivation can be well controlled during post anneal at 400 °C–600 °C. This is achieved by locating the preamorphization induced end of range defects close to the Buried OXide (BOX), thus benefiting from the defect cutting off and sinking effect of the BOX. This offers the opportunity to use LT-SPE activation for dopant activation of the bottom and top FETs in LT 3D sequential integration. In addition, this allows ultra shallow junction to effectively beneficiate from an activation which is higher with LT SPE than with conventional high temperature (HT) spike anneal (1050°C). LT SPE B-doped ultra shallow junction (∼10nm) with a sheet resistance of 900 Ω/┚ was achieved, fulfilling the ITRS requirement for device scaling, down to 22nm node (1100 Ω/┚).
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