Fault-tolerant switching element for the twin butterfly

Abstract

We introduced the twin butterfly as a fault-tolerant low-contention multistage interconnection network at last year's annual meeting. The twin butterfly is the superposition of a randomly permuted butterfly on a regular butterfly. Fault tolerance is essential for the reliable operation of a large network, while low contention is important for its performance. In this presentation, we first consider the switching element design that will support efficient parallel testing of the twin butterfly. The compile-time testing allows computer generated holograms that will route around faulty switching elements after fabrication and overcomes system yield problems. We then show how the switching element is also designed to support off-line testing after the system is packaged. Since the modulators and detectors of the internal switching elements in a packaged system are not directly controllable and observable, off-line system testing is designed such that switching elements check each other and attempt to mask out detector failures. During reconfiguration, switching elements with modulator faults or excessive amount of detector faults will be declared faulty and removed from active operation Note that neither packet routing nor configuration requires a dedicated routing host. VHDL simulation is in progress to verify the design as well as demonstrate system operation.