Fault-Tolerant Quasi Delay Insensitive Combinational Circuits in Commercial FPGA Devices

Abstract

Fault tolerance design is an increasing concern due to VLSI technology scaling, which implements more complex systems in a single chip. Each transistor in such systems is more susceptible to the effects of high-energy particle strikes, mainly in reduced power supply applications. Glitches in any node of the circuit caused by a soft error may propagate or even captured by a memory cell components. In FPGA, this issue is particularly concerning because, in such target devices, any digital circuitry is modeled using programmed LUTs (Look Up Tables) where a flipped bit cannot be recovered unless new programming on it. The proposed architecture for combinational circuits in FPGA devices enhances robustness to a QDI (Quasi-Delay Insensitive) digital design inserting a novel output register based on gates that validate each dual-rail variable the system according to the current processing cycle. The reduced penalties in area, power, and latency for the proposed fault-tolerant architecture are interesting compared to Triple Modular Redundancy (TMR), and Dual Modular Redundancy (DMR) approaches.