Abstract
Quantum error correction requires the detection of errors by reliable measurements of suitable multi-qubit correlation operators. Here, we experimentally demonstrate a fault-tolerant weight-4 parity check measurement scheme. An additional 'flag' qubit serves to detect errors occurring throughout the parity measurement, which would otherwise proliferate into uncorrectable weight-2 errors on the qubit register. We achieve a flag-conditioned parity measurement single-shot fidelity of 93.2(2)\%. Deliberately injecting bit and phase-flip errors, we show that the fault-tolerant protocol is capable of reliably intercepting such faults. For holistic benchmarking of the parity measurement scheme, we use entanglement witnessing to show that the implemented circuit generates genuine six-qubit multi-partite entanglement. The fault-tolerant parity measurement scheme is an essential building block in a broad class of stabilizer quantum error correction protocols, including topological color codes. Our hardware platform is based on atomic ions stored in a segmented microchip ion trap. The qubit register is dynamically reconfigured via shuttling operations, enabling effective full connectivity without operational cross-talk, which provides key capabilities for scalable fault-tolerant quantum computing.
Highlights
We experimentally demonstrate a fault-tolerant weight-4 parity-check measurement scheme, where one additional flag qubit serves to detect errors, which would otherwise proliferate into uncorrectable weight-2 errors onto the qubit register
This stabilizer code [48] encodes k 1⁄4 1 logical qubit into n 1⁄4 7 physical qubits and can correct up to t 1⁄4 ðd − 1Þ=2 1⁄4 1 arbitrary error on any of the physical qubits. This is guaranteed provided that quantum error correction (QEC) cycles are realized via fault-tolerant operations as we outline below, based, e.g., on the flag-qubit-based FT parity-check measurements (PCMs) measurement demonstrated in this work
Postselecting the syndrome measurement on the flag readout, i.e., taking only shots with flag result MðfXÞ 1⁄4 −1 into account, we obtain a conditional parity fidelity of P 1⁄4 93.2ð2Þ%. It exceeds the bare parity fidelity by 4.5 standard errors, showing that the FT scheme operates in the regime where it can catch intrinsic weight-2 errors occurring throughout the PCM sequence
Summary
Quantum computers promise to outperform classical processors for particular tasks [1–4]. Error syndrome readout permits detection of errors through quantum nondemolition parity-check measurements (PCMs) on the logical qubits [6–9]. Such a PCM requires performing a sequence of entangling gates between a set of data qubits and auxiliary qubits, to which the parity information is. We employ a trapped-ion quantum processor to demonstrate a flag-based weight-4 FT PCM scheme, which reduces the overhead for FT syndrome readout to two auxiliary qubits termed syndrome and flag. The flag qubit detects hook errors, i.e., faults occurring on the syndrome qubit that proliferate onto the data-qubit register These remain undetectable in a non-FT PCM scheme and eventually result in a logical error
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