Fault-Tolerant Memory Architecture Against Radiation-Dependent Errors: A Mixed Error Control Approach

Abstract

We present a high qualitative reconfigurability method for fault-tolerant memory systems against radiation influence on semiconductors. Its novelty lies in a joint failure repair mechanism. It uses a concurrent on-line technique based on asynchronous built-in current sensors (BICS), parity check and cold spare modules against electrical abnormal behaviour due to latch-up (LU), and the Hamming SEC code to counterattack single error upset (SEU), manifested in logical failures. Complete reliability computations, which underlie the proposed scheme, search for a 99.902% tolerance, thought to meet typical spatial irradiation conditions, to the cost of a small hardware overhead (2 spare (additional) 1K1 modules for each 1K16 of a memory system of 512K16, and Mean Time To Failure e 10−7 h−1). Finally, as we envisage a 2.4 μm CMOS implementation, we performed complexity estimations, which show that the supplementary self-tolerance ensuring circuitry involves an overhead of 0.0094% for a 512K16 memory. The recovering latency is minimised. For SEU in DRAM it requires zero latency and no more than the duration of an equivalent refresh cycle in SRAM. LU reflects a locality property, as only the affected module is submitted to the recovering algorithm.