Fault tolerant bus architecture for deep submicron based processors

Abstract

In the Deep Submicron era testing of processors is gaining prominence due to the effect of many analog faults. These faults have a direct impact on the signal integrity in interconnects. In deep submicron based processors electromigration poses a major challenge for interconnect reliability. This is of major concern in processor bus architectures. Though a lot of research has been focused on fault tolerance at the module level, no effective research has been carried out to evolve fault tolerant interconnect structures. Faults due to electromigration give rise to weak ones and zeros, thus affecting the signal integrity. This paper presents a fault tolerant scheme for electromigration which also leads to unification of detection and correction of crosstalk faults and stuck-at faults. In the scheme presented, the signal is rerouted through adjacent spare interconnects. The spare interconnect also acts as a shield against crosstalk under fault free system operation. Moreover, the entire testing process is carried out concurrently with the processor instruction execution. The hardware overhead is also insignificant compared to the overall device count in a deep submicron based processor. To the best of our knowledge this is the first time a fault tolerant scheme for bus architectures is being presented.