Fault Tolerant Analysis of Single Phase Multilevel Inverter

Abstract

Low reliability of semiconductor switches result in the maloperation of the multilevel inverter (MLI). In order to gain the advantages offered by the MLI without compromising on the reliability, a fault tolerant topology of MLI is required. In this paper, the switched capacitor MLI (SCMLI) structure is explored to extract its inherent capacity for single switch and multiple switch failure. In order to incorporate fault tolerant characteristics to a 9 level SCMLI structure, the outermost capacitor is substituted by the DC voltage source. This results in the ability of the SCMLI to tolerate both single and multiple switch failure across all its level generating switches. Proper implementation of the switching scheme results in inherent capacitor voltage balancing. All the employed switches in the architecture of the topology of main inverter are fault tolerant. Least modification in the switching scheme after fault occurrence and less number of active switches makes the modified SCMLI topology more reliable with reduced device count. Assessment of the viability and robustness of the topology is verified through MATLAB simulation and experimentally validated using real-time simulator, OPAL-RT.