Fault tolerance for arithmetic and logic unit

Abstract

Very large scale integration (VLSI) technology has evolved to a level where large systems, previously implemented as printed circuit boards with discrete components, are integrated into a single integrated circuit (IC). But aggressive new chip design technologies frequently adversely affect chip reliability during functional operation. Reliability is of critical importance in situations where a computer malfunction could have catastrophic results. Reliability is used to describe systems in which it is not feasible to repair (as in computers on board satellites) or in which the computer is serving a critical function and cannot be lost even for the duration of a replacement (as insight control computers on an aircraft) or in which the repair is prohibitively expensive. The use of concurrent error detection scheme with order to achieve the high reliability requirement of modern computer systems is becoming an important design technique. The present paper describes implementation of error-detection mechanisms for detecting faults within the Arithmetic Logic Unit (ALU). The Boolean unit of the ALU uses duplication of hardware with comparison as the error detection mechanism. The arithmetic unit of the ALU uses residue codes as the error detection mechanisms. If a fault is detected in the ALU we have to replace it with the spare ALU which will make error correction possible. We will compare this fault tolerance mechanism with the current fault-tolerance mechanisms (Triple redundancy with single voting scheme and Triple modular redundancy with triplicated voting mechanism).