Fault simulation for VHDL based test bench and BIST evaluation

Abstract

A VHDL based Fault simulation procedure for test bench and test hardware evaluation has been developed. This work is aimed to utilize features of VHDL for more efficient fault simulation. Information about fault detection can be obtained in this environment using fault simulation method and guidelines presented in this report. This environment consists of automated steps, which will lead to fault simulation. Information such as fault coverage, efficiency of test patterns and capability of test hardware to detect faults, can be extracted. Using this environment, one can evaluate test benches and order test vectors or configure BIST (Built-In Self Test) architectures.