Fault Models for Logic Circuits in the Multigate Era

Abstract

With increased scaling to lower technology nodes, the electrostatic integrity of planar FETs is expected to worsen, necessitating the adoption of low-leakage high-performance multigate FETs, amongst which the FinFET is very attractive with respect to fabrication process complexity. A significant void from a circuit testing viewpoint is the absence of fault models for FinFETs. In particular, it is unclear if CMOS fault models are comprehensive enough to model all defects in FinFET circuits. We investigate the aforementioned problem using mixed-mode FinFET device simulation and demonstrate that while faults defined for planar FETs show significant overlaps with FinFETs, they do not encompass all regimes of operation. Results indicate that no single fault model can adequately capture the leakage-delay behavior of logic gates based on independent-gate FinFETs with opens on the back gate, and shorted-gate FinFETs, which have been accidentally etched into independent-gate structures. To this effect, we categorize back-gate cuts into three regimes where either pulse broadening or pulse shrinking occurs, which can be tested using three-/two-pattern delay fault tests.