Abstract

As the device characteristic size become tiny, the failure mode shall be more complex and challenging. Traditional isolation techniques such as photon emission microscope (PEM) and optical beam induced resistance change (OBIRCH) are not effective to localize the explicit defect in tremendous complexity cases. Therefore, the advanced dynamic EFA techniques are definitely required. In this study, a novel and effective dynamic analysis technique (DAT) was proposed, which combines PEM and evaluation board to determine the failure location specifically. In 5nm logic device, this method has been successfully applied to diagnose the failure location and identify functional failure mode of SerDes module leakage during testing at low temperature. Eventually, the results showed that DAT could localize the failure site immediately and accurately. Recently, the manufacturing of silicon node had been scaling down dramatically, we would keep on DAT development for the next generation semiconductor devices.

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