Fault injection test bed for clock violation or metastability based Cipher attacks on FPGA hardware

Abstract

In this project an FPGA based test bed is realized for injecting faults through clock glitches, to result in setup and hold violations. The UART interface is realized on FPGA to provide PC based controlling for this fault injection. The pre-build serial International Data Encryption (IDEA) algorithm synthesis models will be used as test encryption algorithm. The Xilinx Digital clock manager (DCM) component will be used for generation clocks of different frequencies and phase shifts. The encryption module output with faults introduced and without fault introduced is compared as a function of ratio of used clock frequency and maximum frequency of operation reported by synthesis tool. The modules for clock generation, clock switching, interface adopter to IDEA core and UART interface will be realized and tested in FPGA hardware in integrated form. From PC using HyperTerminal commands will be sent to FPGA firmware. Xilinx simulation and synthesis tools are used to this project. Xilinx Spartan family FPGA board along with serial communication with PC will be used for hardware level testing. Xilinx chipscope tools will be used for verifying the output at various levels in FPGA hardware.