Fault detection and diagnostic tests for logic gates

Abstract

The paper is concerned with the problems of repair check and diagnosis of states of N logic gates that realize, in working condition, a given Boolean function f(x 1 , . . . , x n ). This problem is attacked by composing single-output circuits from the given logic gates and then observing the values produced by these circuits on various arbitrary input families of values of the variables. Arbitrary constant faults at the outputs of logic gates are admissible.Moreover, it is assumed that at most k gates are faulty, where k is a given natural number not exceeding N. It is required to minimize the number of circuits used to check the repair status and determine the states of all logic gates. It is proved that if f ∉ {x 1 & . . .&x n , x 1 V.. . ..Vx n , x̅ 1 } and if k and N satisfy some condition, then 2k + 1 circuits are capable of checking the repair status of all the gates. If, additionally, the function f is nonlinear, then 2k + 1 circuits are sufficient to diagnose the states of all the gates.